1. Field of the Invention
The present invention relates to a semiconductor device with a power saving function.
2. Description of the Related Art
Very recently, synchronous DRAMs (Dynamic Random Access Memories) capable of achieving high-speed access operations and high data bandwidths have been marketed in 16-Mbit generation and further 64-Mbit generation. In such a synchronous DRAM, all of memory operations thereof are performed in synchronous with a external clock signal CLK. Also, the synchronous DRAM is typically provided with a power down mode to reduce current consumption of an input buffer.
FIG. 1 is a diagram showing the structure of a conventional synchronous DRAM with such a power down mode. Referring to FIG. 1, in this conventional synchronous DRAM circuit, a clock signal CLK is supplied to an input buffer circuit 51b, a chip select signal CSB is supplied to another input buffer circuit 51c, and a row address strobe signal RASB is supplied to another input buffer circuit 51d. Also, a column address strobe signal CASB is supplied to another input buffer circuit 51e, and a write enable signal WEB is supplied to a further input buffer circuit 51f. Address signals A0 to A11 are supplied to the input buffer circuit 51h, and data signals DQ0 to DQ15 are supplied to the input buffer circuit 51i.
A combination of three types of signals such as the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB gives one of various types of commands. For example, a data write command CMD and a data read command (CMD) may be applied to an SDRAM. The address signals A0 to A11 are applied in combination with commands CMDs, so that addresses of memory cells are designated. Furthermore, a mask signal U/LDQM is supplied to the input buffer circuit 51g. This mask signal U/LDQM causes the data D0 to D15 not to be read out from the SDRAM, or causes the data D0 to D15 not to be written into the SDRAM.
On the other hand, a clock enable signal CKE is supplied via another input buffer circuit 51a to a power down control circuit 52. In response to the clock enable signal CKE, the power down control circuit 52 generates power down signals PWDNB and PWDNBQ. The power down signal PWDNB is supplied to these input buffer circuits 51b, 51c, 51d, 51e, 51f, 51g and 51h, whereas the power down signal PWDNBQ is supplied to another input buffer circuit 51i.
As shown in FIG. 4, each of the input buffer circuits 51b to 51h of each of the SDRAMs is composed of a current mirror type pre-stage circuit 71 and a buffering circuit 72. When the power down signal PWDNB is in a high level, the current mirror type pre-stage circuit 71 is set to an active state. Conversely, when the power down signal PWDNB is in a low level, the current mirror type pre-stage circuit 71 is set to a power down state. The current mirror type pre-stage circuit 71 operating in the active state continuously consumes a current passing from a power supply potential Vcc to the ground potential GND through P-channel type transistors 71a, 71b, and 71c and N-channel type transistors 71d, 71e, and 71f. The passing-through current will be referred to as a "DC current" hereinafter. Symbol "Vref" indicates a reference signal used to determine whether a level of a command CMD is in a low level or a high level. The level of the reference signal Vref is in an intermediate level between the power supply potential Vcc and the groudn potential GND. The buffering circuit 72 is provided to transfer a command CMD with a high level or a low level to an internal circuit of the SDRAM. The buffering circuit 72 operates only when the current mirror type pre-stage circuit 71 is set to the active state, and consumes a current when the level of the command CMD is switched from the high level to the low level, or vice versa. The current consumed by the buffering circuit 72 at that time will be referred to as an "AC current" hereinafter.
Now, a current consumption condition in the conventional synchronous type semiconductor memory system will be described below. As shown in FIG. 1, each of these SDRAMs determines whether the power down signal PWDNB supplied from the power down control circuit 52 is in the high level or the low level, depending on the input state of the clock enable signal CKE. That is, when the clock enable signal CKE is in the high level, the power down signal PWDNB becomes the high level, so that the input buffer circuit operate. Conversely, when the clock enable signal CKE is in the low level, the power down signal PWDNB becomes the low level, so that the input buffer circuit does not operate. The data signals DQ0 to DQ15 shown in FIG. 1 are supplied with the power down signal PWDNBQ which is a inversion signal of the power down signal PWDNB. Even if the clock enable signal CKE is in the high level, the power down signal PWDNBQ becomes the low level. Therefore, when a reading command CMD is supplied, the data signals DQ0 to DQ15 can be accessed.
FIG. 2 shows an example of an arrangement of a memory system in which n SDRAMs each having the structure shown in FIG. 1 are mounted. As shown in FIG. 2, a plurality of SDRAMs 61 to 6n are provided in a memory system. A chip select signal CSB is supplied to specify one of the SDRAMs for a command CMD to be applied. It should be noted that an address signal A, a mask signal U/LDQMB, a data signal DQ, a command CMD, a clock CLK, and a clock enable signal CKE are commonly used to the n SDRAMs 61 to 6n. As an exceptional case, the respective SRAMs has the specific signal lines for the chip select signals CSB. Thus, the respective chip select signals CSB1 to CSBn are supplied to the respective SDRAMs 61 to 6n.
FIGS. 3A to 3G are timing charts showing an example of operations of the SDRAM memory system. When the level of the clock signal CKE becomes high as shown in FIG. 3A, the power down signals PWDNB1 to PWDNBn for synchronous type memories 61 to 6n become high as shown in FIG. 3C. In case that a command CMD of "ACT-1" shown in FIG. 3G is applied to the synchronous type memory 61, the chip select signal CSB1 is set to a low level. When the clock signal CLK for the chip select signal CSB1 is in the high level, the command CMD of "ACT-1" is applied to the SDRAM 61 only while the chip select signal CSB becomes a low level. Similarly, when a command of "ACT-2" shown in FIG. 3E is applied to the synchronous type memory 62, the chip select signal CSB2 becomes low. Other synchronous type memories are controlled in a similar manner. At that time, the synchronous type memories 61 to 6n continuously consume a DC current while the clock enable signal CKE is in the high level, and also the power down signals PWDNB1 to PWDNBn become high. Also, when the command CMD is switched between the high level and the low level, an AC current is consumed in the synchronous type memories 61 to 6n, irrespective of the DC current.
In this way, in the conventional SDRAM system, although a command is applied to one of SDRMs of the memory system, other SDRAMs also consume currents.
In conjunction with the above description, a power cutting circuit for a synchronous semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-177015). In this reference, a power cutting circuit (11, 12, 13 and 14) cuts the power supplied to an input initial stage circuit connected to external input/output pin in a standby state or in a reading operation. Also, when an input is supplied to another input pin to make the output of the external input/output pin invalid, the power cutting circuit powers on the input initial stage circuit. Thus, consumption current is reduced by cutting the power supplied to the input initial stage circuit in a mode other than a power down mode in a synchronous-type DRAM.
Also, a power down memory control unit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-273355). In this reference, a control timing generating circuit (1) stops the issue of a control timing signal to a memory module set to a use impossible state by a user. A gate control circuit 2 generates a gate signal to gate circuits (7) to (10) to gates clocks signal so that the supply of the clock signal to the use impossible memory module is restrained. DRAMs (3) to (6) recognize the use impossible state when the supply of the clock signals are restrained, and stops the operation. then, the DRAMs carry out enforced refreshing operation at a constant period. Thus, when a memory module of the DRAMs is set to the use impossible state, the reduction of power consumption, the preservation of data and the overhead removal in case of use resumption can be attained.
Also, a synchronous-type semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-69285). In this reference, the synchronous-type semiconductor memory device can take either of a CSUS mode and a power down mode (PD mode) to make a predetermined circuit operation invalid when the memory device operates in synchronous with a clock signal which is externally supplied, and an external signal CKE is in a high level. A signal generation circuit (120) generates an internal signal (rasdz signal) which is switched from a first state to a second state at the timing with a predetermined delay after an internal RAS signal (rasdz signal) is switched from the first state to the second state. The internal RAS (rasdz signal) can take the first state and the second state in which the non-output state of data is permitted. A timing control circuit (104) makes a power down mode (PD mode) valid in synchronous with the clock signal when the internal signal (rasdz signal) generated by the signal generating circuit (120) takes the second state while the above external signal CKE is in the high level. Limitation to input timing of the external signal is released as less as possible.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-66842). In this reference, a power down control circuit (52) generates a power down control signal PDENTRn which is in a low level during a refreshing operation at least, from a signal CONT.PIN which is generated based on the outputs of buffer circuits of a semiconductor memory device and defines a period of the refreshing operation. The power down control signal PDENTRn is supplied to the buffer circuits (41 to 46, 48 and 49). The buffers of an input reception section (1) other than a CKE buffer in which the power down control signal PDENTRn is in the low level are fixed to a low level to never receive input signals to external pins. Thus, only a circuit necessary for the refreshing operation operates so that power consumption can be reduced.
Also, a semiconductor memory unit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-66849). In this reference, a power down control circuit (14) sets a power down signal /PDENTR to a high level to release a power down mode when a clock enable signal CKE asynchronous with a clock signal goes to a high level. When the power down mode is released, a clock control circuit (13) release a mask signal /CLKMSK and a clock driving circuit (12) outputs an internal clock signal CP1 to enable an output of a command decoder (43) to be latched.
Also, selective power down for a high performance CPU/system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-505244corresponding to WO93/20498). In this reference, a microelectronic apparatus is composed of two functional units formed on a single chip or die. In execution of a computer program for controlling the microelectronic apparatus, all the units do not operate at a time. Therefore, each of the units is turned on or off based on the executed program. This is achieved through one of the following three schemes: stopping the supply of a clock signal to a functional unit, stopping the supply of power to the functional unit, and stopping the supply of an input signal to the functional unit.